A typical flash memory device can include a stacked structure including a floating gate. A method for fabricating a conventional gate structure of a nonvolatile memory device is described below with reference to FIG. 1. Referring to FIG. 1, a gate pattern 90 of a nonvolatile memory device is formed on an integrated circuit substrate 10. The gate pattern 90 includes a gate oxide layer 12, a floating gate 14, an inter-gate dielectric 21, a control gate 22, and a capping pattern 24 formed in sequence. The gate oxide layer can be a silicon oxide layer that is formed by thermally oxidizing the substrate 10. The inter-gate dielectric 21 can be made of a lower silicon oxide layer 16, a silicon nitride layer 18, and an upper silicon oxide layer 20, which can be formed in sequence. The floating gate 14 can be made of polysilicon, the control gate 22 can be made of polysilicon, and a silicide can be formed in sequence.
The gate pattern 90 can be formed by dry etching using a plasma. The plasma dry etch may damage the gate pattern 90, which may have an adverse effect on characteristics of the nonvolatile memory device. The damage from the plasma dry etch may be repaired by thermally oxidizing the gate pattern 90 to form a silicon oxide layer on sidewalls of the floating gate 14 and the control gate 22.
The thermal oxidation process can be carried out in an oxygen atmosphere at high temperature. The thermal oxidation process can cause the edges of the inter-gate dielectric 21 and gate oxide layer 12 to thicken, which can reduce a coupling ratio between the control gate 22 and the floating gate 14. The coupling ratio can reflect the efficiency of a transfer of voltage applied to the control gate 22 to the floating gate 14. Therefore, a reduced coupling ratio may necessitate increasing voltages used to operate the nonvolatile memory device.
It is known to form a gate of a nonvolatile memory device using a diffusion barrier layer as disclosed in Korean Patent No. 2001-0004263, the content of which is incorporated herein by reference. FIGS. 2 and 3 are cross-sectional views illustrating conventional methods of forming nonvolatile memory device using a diffusion barrier layer as discussed in Korean Patent No. 2001-0004263.
Referring to FIG. 2, steps performed before and after a thermal oxidation process, i.e., a step of forming a gate pattern 90, can be the same as discussed above in reference to FIG. 1. Following formation of the gate pattern 90, a lower insulation layer 28 and an upper insulation layer 30 can be formed to cover an entire surface of the gate pattern 90. The lower and upper insulation layer 28 and 30 can be made of silicon oxide and silicon nitride, respectively.
The integrated circuit substrate, including the upper insulation layer 30 is thermally oxidized. The upper insulation layer 30 can provide a diffusion barrier layer that covers an entire surface of the substrate including the gate pattern 90, which can reduce or prevent the amount of oxygen atoms that reach the gate pattern 90 during the thermal oxidation process.
However, while the thermal oxidation process discussed in reference to FIG. 2 may repair damaged portions of the structure, the process may not improve the shape of the floating gate 14. The shape of the floating gate 14 can be improved as shown in FIG. 3. Referring to FIG. 3, the upper and lower insulation layers 30 and 28 can be successively removed to expose the gate pattern 90. A spacer layer is formed to cover an entire surface of the substrate including the exposed gate pattern 90. Generally, the spacer layer can be a silicon oxide layer that is formed by Chemical Vapor Deposition (CVD). The spacer layer can be anisotropically etched down to a top surface of the gate pattern 90 to form a gate spacer 32 on a sidewall of the gate pattern 90.
Because the gate spacer 32 is a silicon oxide layer that is formed by means of CVD, the electrical characteristics of the gate spacer 32 may be inferior to those of the gate oxide layer 12 formed by the thermal oxidation process. Since the floating gate 14 is protected from oxidization by the spacer 32 during the process, a lower edge 60 of the floating gate 14 may retain an angular shape and, therefore, charges stored on the floating gate 14 may be close to the gate spacer 32. The inferior electrical characteristics of the gate spacer 32 may cause electrical charges, that are otherwise accumulated on the floating gate 14, to more readily leak. Furthermore, an electric field may concentrate at the lower edge 60 of the floating gate 14 due to its angular shape, thereby possibly further increasing leakage in the nonvolatile memory device.